The impact of back-side Cu contamination on 3D stacking architecture

Abstract

Three-dimensional (3D)-stacked Si chip architecture using Cu through-silicon vias can make microelectronic devices vulnerable to Cu contamination. In this article, 130 nm complementary metal oxide semiconductor devices were used to investigate back-side Cu contamination. Cu was deposited directly on the back side of thin wafers, which were further annealed at 350° C. No prominent degradation was observed for key device parameters. A multilayer of Cu/ SiO2 (400 nm)/Si was revealed by focused ion beam-scanning electron microscopy, and transmission electron microscopy. X-ray diffraction was conducted on a blank wafer to study the interaction between Cu and Si. The exceptional growth of silicon oxide at room temperature is explained by a partial reconstitution mechanism of the catalytic Cu3 Si. © 2009 The Electrochemical Society.