Static timing analysis and timing violations of sequential circuits

Abstract

Designing of sequential circuits needs timing analysis at each and every stage of design process (synthesis, floor planning, placement, routing, layout design…) and comprises of three main parts-Timing checks, Constraints and Libraries. Timing checks such as setup (Ts) and hold time (Th) violation check in sequential circuits plays an important role during timing verification. This paper describes about static timing analysis mainly about reg2reg setup and holds analysis and analyses a kind of detection and correction circuits for Ts and Th violations [1] by associating a digital circuit to them.