Design of fast efficient radix-16 sequential multiplier

Abstract

Multiplication is an important function in computer arithmetic operations. The multiplication process will be done by the shift-and-add sequential multiplication procedure. Radix-16 sequential multiplier design generates the radix-16 partial products as two low (L) and high (H) components. In order to reduce cycle time, Brent-Kung adder and two radix 16 carry-save adders are used to generate radix-16 partial products. The proposed design of radix-16 sequential multiplier is efficient over previous designs and comparison depicts ADP and PDP of existing method are 11.22% and 8.45% than proposed method. However, the Excess area-Delay product and Excess-power-Delay product is also lowered. The design is carried out in Xilinx ISE 14.5 software and cadence tool for simulation and synthesis results. Fast efficient radix-16 sequential multiplier can be used in many digital signal processing applications.