High Power and High Frequency CMOS Oscillator with Source-to-Drain Coupling and Capacitive Load Reduction Circuit

Abstract

A design for a high-output-power, high-frequency CMOS oscillator is presented in this paper. The proposed oscillator can increase the output power by coupling the signal at the source of the core transistor to the drain of the buffer transistor. In addition, the source-to-drain coupling generates an optimum negative transconductance at the desired operating frequency. A capacitive load reduction circuit is also applied to increase the fundamental oscillation frequency. Using these techniques, the fundamental and push-push oscillators were implemented using 65 nm CMOS technology. The measurement results of the fundamental and push-push oscillators showed 2.7 and -25 dBm of peak differential output power at 194 and 394 GHz, respectively. In the 200 GHz frequency band, the proposed fundamental oscillator shows the highest output power among recently reported state-of-the-art CMOS oscillators.