Design and performasnce analysis of hybrid full adder using finfet 40nm technology

Abstract

Designing a low power and energy efficient circuits in FinFET technology is of great Challenge. This paper presents the internal logic structure and circuit operation using the devices, CMOS and FinFETs for designing the hybrid adder cells. At transistor level, CMOS and FinFET based hybrid full adder (HFA) and improved hybrid full adder (IHFA) is designed. Simulations are carried out using the cadence tool in UMC 40nm and the performance analysis of these HFA and IHFA are compared with the 40nm FinFET technology. It is observed that IHFA is better when compared with the HFA in terms of propagation delay, power consumption and energy delay product. IHFA achieves the higher drive current and low leakage power for better mobility and transistor scaling as compared with HFA.