Implementation of Transistor Stacking Technique in Combinational Circuits

Abstract

This paper deals with the reduction of power dissipation in the basic logic circuit like NAND gate and NOR gate by using transistor stacking technique. The logic gates are designed using 130nm technology parameter and are simulated using PSPICE. The input vector combinations are compared with the simulated result on the basis of propagation delay and power consumption. It is found that when the number of low-input increases in case of NAND gate the power dissipation decreases but the delay increases and for NOR gate power dissipation decreases with the increase in high input vector combinations.