Design of asymmetrical doherty power amplifier with reduced memory effects and enhanced back-off efficiency

Abstract

This paper presents the design of an asymmetrical Doherty power amplifier (DPA) with improved linearity and efficiency performance. Resonator-type drain bias networks, providing high impedances at the carrier frequency and low impedances with small variation at the envelope frequency, are introduced to reduce the DPA’s memory effects when transmitting wideband signals. The general criteria for DPA design are summarized, and the approach to obtain optimum fundamental and harmonic impedances is proposed to achieve back-off efficiency enhancement. For experimental validation, the asymmetrical DPA is designed and implemented using two identical GaN HEMTs. Measured with continuous wave (CW), the proposed DPA delivers a saturation power greater than 49.3 dBm from 3400 to 3600 MHz, along with high drain efficiency of over 62% and 48% at peak and 8-dB back-off power, respectively. Driven with 100-MHz LTE-advanced signals, the adjacent channel leakage ratio (ACLR) asymmetry of the DPA at 20-MHz offset is lower than 1-dB. After digital predistortion (DPD) linearization, the proposed DPA achieves an ACLR of better than −48 dBc at an average output power about 41 dBm and the drain efficiency over 45% across the frequency band.