Influence of Process Parameter on Carbon Nanotube Field Effect Transistor Using Response Surface Methodology

Abstract

Carbon nanotube field-effect transistor (CNTFET) is a good option to replace silicon for low power consumption application. Recent research shows that CN-FET thermal and electrical properties alter with length, diameter, and gate parameters. Optimization of CNTFET design parameters helps control some of the factors. Double gate and cylindrical gate layouts are introduced to overcome these facts. Carbon nanotubes have an intercapacitance between them that increases as their diameter increases. Total capacitance and inductance of CNTFETs increase with nanotube count. In order to reduce the voltage drop between semiconducting and metallic terminals, the diameter and pitch must be raised. This study employs response surface methodology and ANOVA technique that were used to optimize CNTFET process parameters. Thickness, voltage, delay, and power were all considered. The most affecting parameter was investigated.