A varying processor cache sets architecture

Abstract

Any processor cache has three parameters capacity, line size and associativity. Usually all three are fixed at design time. Algorithms to have variable cache sets are proposed in literature. This paper proposes a method to have variable cache sets logically. The cache comes with fixed sets. The cache is visualized to have logically any number of sets greater than or equal to one. An algorithm for line placement/replacement is proposed in this paper for this model. The proposed model is simulated with SPEC2K benchmarks using Simplescalar Toolkit for two level inclusive set associative cache system. A power saving of 8.4% for L1 cache size 512x4, 17.58% for 1024x4 and 31.3% for 2048x4 is observed compared with traditional set associative cache of same size. A power saving of 7.53% compared with model proposed in literature for L1 size 512x4, 7.64% for 1024x4 and 7.645% for 2048x4 is observed. The L2 cache size is fixed at 2048x8. The average memory access time (AMAT) is found to degrade compared with conventional set associative cache by 19.63% for L1 size of 512x4, 24.68% for 1024x4 and 2048x4. (Abstract).