A Fault Tolerant Han-Carlsonadder using Tmr Technique

Abstract

A fault tolerant Han-Carlson adder is implemented using TMR technique. This paper suggests a technique of Triple Mode Redundancy (TMR) in which the vote is processedto produce a single output by a majority voting system.Synthesis and simulation are performed using Vivado(Xilinx). The circuitry is basically repeated in triplicate, as the name suggests, with a voting circuit used to transmit to the output the majority rule signals.