Submodule capacitance requirement reduction with capacitor voltage ripple suppression in MMC

Abstract

In modular multilevel converter (MMC)-based high-voltage direct current transmission system, hundreds of submodules (SMs) with large SM capacitance in each arm result in expensive cost and bulky volume. In full-bridge submodules (FBSMs)-based MMC (FB-MMC), a novel capacitor voltage ripple suppression method based on three available variables manipulation is proposed to reduce SM capacitance requirement. In the interaction of these available variables, the dominant fundamental-frequency and second-order harmonic fluctuations of SM capacitor voltage can be eliminated under different power factors. Under the proposed method, three-to-five times frequency fluctuation components will be reduced as much as possible. By establishing capacitor voltage fluctuation model, the concrete mathematical expressions of the three desired available variables under different power factors can be derived, which are easily implemented to suppress capacitor voltage ripple. Compared with normal operation, SM capacitor voltage ripple can be reduced by 80% with the proposed method when the power factor of 0.9-1 is considered. In other words, SM capacitance requirement can be reduced by 80% under the same constraint of capacitor voltage ripple. Therefore, the cost and volume of SM capacitors can be significantly reduced. Simulation results confirm the feasibility and validity of the proposed method.