Efficient design space exploration in PICO

Abstract

Automated design tools must understand and exploit the hierarchical structure of large design spaces. We have developed a general methodology for decomposing system design spaces into smaller component design spaces, followed by component-level evaluation, filtering, recomposition and system-level evaluation. This methodology greatly reduces the time and cost of design space exploration, since the typical number of system-level evaluations is greatly reduced. This paper describes the application of our decomposition methodology in the context of PICO. PICO is a design space exploration system that automatically generates embedded designs consisting of a stylized processor, hardware accelerator and a cache hierarchy, each customized to a benchmark. First, PICO splits the specified system design space into smaller design spaces, one for each of the components, viz. processor, accelerator and data/instruction/unified caches. PICO further partitions each component design space into predicated design spaces, so that all designs in a predicated design space satisfy a specified predicate. PICO uses component-level evaluations to identify the performance-cost optimal component-level Pareto designs in each predicated design space. PICO generates all compositions of Pareto designs from compatible predicated design spaces and uses a system-level evaluation to identify the Pareto designs at the system level. For reasonable design spaces, PICO reduces the design exploration time by over four orders of magnitude compared to an exhaustive approach.