Topological exploration for the efficient design of three-dimensional Network on Chip architectures

Abstract

With the advent of nanoscale computing the new era of communications demand IC technologies with lesser silicon footprint, low power consumption and higher bandwidths. There has been a paradigm shift from conventional bus based approach to Network on Chip (NoC) approach because of technology constraints. The NoC technology with shorter wires and layered structured forms the 3D Network on Chip which forms a promising and emerging field of research. Architecture of 3D NoC's, Topologies, Interconnects, Routing of 3D NoC's are indeed novel areas of exploration. The 3D IC's enable the optical devices, analog circuitry and digital circuitry in three different layers which is a unique feature to develop highly heterogeneous and multifunctional systems. This paper discusses about the basics of NoC's, 3D NoC's layout and detailed description of 3D NoC Topologies. All the distinct features of Topologies are listed and clustered Topologies seem to be the promising Topologies for nano scale design if clock and thermal issues are to be overcome with proper approach in 3D NoC's.