Characterization of Novel 8T SRAM with Low Leakage and Optimized Area

Abstract

The fast evolution of battery functioned devices has caused approaches for decreasing power consumption in the memories is substantial. In this paper, a new proposal of SRAM with 8 transistors (8T) has been designed and also the cell itself is tested for its unique data overwriting and read propagation delays around 13.33% (read ‘1’) and 3.58% (read ‘0’) less compared to a conventional model. As the technology is attenuating, cell stability and increasing noise margin have become two crucial topics for the design metrics of SRAM, where our proposed cell appears with great stability on low voltage operation. Widespread simulation results authenticate the cogency and competency of the proposed 8T SRAM model using Cadence and 45nm predictive technology model (PTM).