Fast Validation of Mixed-Signal SoCs

Abstract

Today's mixed-signal SoCs are challenging to validate. Running enough test vectors often requires the use of event-driven simulation and hardware emulation, which in turn necessitates the creation of analog behavioral models. This paper reviews different approaches proposed to address that modeling challenge, and shows how they can be divided by the methods used to solve for analog circuit values, represent analog waveforms, and validate analog functional models. We illustrate the power of these techniques as applied to a 16 Gb/s PHY, demonstrating a 10,000× speedup vs. SPICE simulation using event-driven models in Verilog simulation, and a further 5,000× speedup using synthesizable analog models in FPGA emulation.