A Hex Itoh-Tsujii inversion algorithm for FPGA platforms

Abstract

The Itoh-Tsujii inversion algorithm forms a major contribution in finding the inverse in cryptographic applications such as Elliptic Curve Cryptography. In this paper, a new Hex Itoh-Tsujii inversion algorithm is proposed to compute the multiplicative inverse efficiently on Field-Programmable Gate-arrays (FPGA) platforms for binary fields generated by NIST recommended irreducible trinomials. The Hex Itoh Tsujii inversion Algorithm based proposed architecture is constructed with hex circuits and quad addition chain. This combination improves the resource utilization. The experimental results shows that the proposed work has better Area-Time Performance compared with the existing implementation. we propose a new Hex circuit to perform the hex exponentiation (A16) in the inverse architecture with reduced area. The inverse algorithm for this architecture follows a Quad addition sequence [21] for irreducible trinomials. It achieves higher Area-Time Performance (ATP) than the existing techniques specified in the literature. In addition, the proposed architecture is scalable for any irreducible trinomial.