Architecture of a dataflow single chip processor.

Abstract

A high-degree-of-parallelism (more than a thousand) dataflow machine called EM-4 is under development. The authors assert that it is essential to fabricate the processing element (PE) on a single chip to reduce operation speed, system size, design complexity, and cost. In the EM-4, the PE, called EMC-R, has been specially designed using a 50,000-gate gate array chip. The authors focus on the architecture of the EMC-R. Its distinctive features are a strongly connected arc dataflow model, a direct matching scheme, and integration of a packet-based circular pipeline and a register-based advanced control pipeline. These features are examined, and the instruction-set architecture and the configuration architecture that utilize them are described.