Analog-Aware Schematic Synthesis

Abstract

In this paper, we present a novel method of analog circuit schematic synthesis, which bridges topology synthesis and circuit sizing & layout synthesis in analog synthesis flow. Compared with traditional schematic synthesis, it brings templates-in, functionality analysis and partitioning for new hierarchy, constraint generation, port analysis, and analog-aware constraint identification into the new schematic synthesis, and enable analog-aware symbol generation for cells, symbol placement, and wire routing based on the functionality, new hierarchy, port types, and other constraints, also the constraints for sizing, floor-planning, and layout optimization are identified on the schematic. Experimental results show that designers can get analog functionality, structural feature, and constraints from the schematic intuitively, which is helpful to designers for sizing, floor-planning, and layout optimization.