Technology mapping for area optimized quasi delay insensitive circuits

8Citations
Citations of this article
5Readers
Mendeley users who have this article in their library.

This article is free to access.

Abstract

Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but do not perform well to automatically synthesize and optimize. This paper presents a new methodology to model and synthesize data path QDI circuits. The model used to represent circuits is based on Multi-valued Decision Diagrams and allows obtaining QDI circuits with two-input gates. Optimization is achieved by applying a technology mapping algorithm with a library of asynchronous standard cells called TAL. This work is a part of the back-end of our synthesis flow from high level language. Throughout the paper, a digit-slice radix 4 ALU is used as an example to illustrate the methodology and show the results. © 2007 Springer Science+Business Media, LLC.

Cite

CITATION STYLE

APA

Folco, B., Brégier, V., Fesquet, L., & Renaudin, M. (2007). Technology mapping for area optimized quasi delay insensitive circuits. In IFIP International Federation for Information Processing (Vol. 240, pp. 55–69). https://doi.org/10.1007/978-0-387-73661-7_5

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free