A novel design of synchronous counter for low power and high-speed applications

Abstract

In this paper, a new power efficient and high-speed synchronous up-counter design suitable for low power and high-speed applications is proposed. The clock gating concept embedded in this design reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem and unwanted switching activities. This design can be used in many applications such as memory systems, microcontroller circuits, frequency dividers etc. The simulation results in Cadence Virtuoso based on CMOS 90-nm technology shows that the proposed design features less power dissipation, and better power delay performance (PDP) when compared with conventional designs. The proposed design is having the advantage of 33.50% in power and 30.66% in speed when compared with conventional design. The proposed counter is implemented in Xilinx Spartan-3 FPGA.