Characterization and modelling of MOSFET operating at cryogenic temperature for hybrid superconductor-CMOS circuits

Abstract

Short channel MOSFET devices have been fabricated using a commercial 0.25 μm CMOS process and characterized at cryogenic temperatures for further application in hybrid superconductor-CMOS circuits. A 4 K device model has been established through modifying the room temperature CMOS model by taking into account the parameter variation of the discrete MOS devices at cryogenic temperature. We have demonstrated that the circuit simulation based on this model is comparable with the measurement at 4 K on a 31-stage ring oscillator both with and without long wire interconnect; therefore, the cryogenic model is acceptable for circuit simulation. Circuit performance at cryogenic temperature has been studied by a set of ring oscillator experiments and a 60-70% improvement of the propagation delay of MOS device and circuit with interconnect wire at 4 K has been reported.