Drive strength aware cell movement techniques for timing driven placement

Abstract

As the interconnections dominate the circuit delay in nanometer technologies, placement plays a major role to achieve timing closure since it is a main step that defines the interconnection lengths. In initial stages of the physical design ow, the placement goal is to reduce the total wirelength, however total wirelength minimization only roughly addresses timing. A timing-driven placement incorporates timing information to remove or alleviate timing violations. In this work, we present an incremental Timing-Driven Placement (TDP) ow to further optimize timing violations via single-cell movements. For late violations, we developed techniques to reduce the load capacitance on critical nets and to obtain load capacitance balancing using drive strength. For early violations, we present techniques that rely on clock skew optimization, register swap and interconnection increase. Our ow is experimentally evaluated using the International Conference on Computer-Aided Design (ICCAD) 2015 Incremental Timing-Driven Contest infrastructure. Experimental results show that our ow can significantly reduce timing violations. On average, for long maximum displacement, the quality of results is improved by 67.8% with late Worst Negative Slack (WNS) and Total Negative Slack (TNS) being improved by 2.31% and 10.84%, respectively, early WNS and TNS improved by 68.92% and 76.42%, respectively and congestion metric Average Bin Utilization (ABU) improved by 74.9% compared to the 1st place in the contest. The impact on Steiner Tree Wirelength (STWL) is less than 2.5%.