Use of a CPLD in an introductory logic circuits course with software and hardware upgrade

Abstract

This paper documents our continued efforts to integrate the use of complex programmable logic devices (CPLD) into our introductory logic circuits course at the University of Hartford. Although programmable logic devices (PLDs) have been long introduced in our advanced courses, the widespread acceptance demands that PLDs be introduced earlier in the electrical and computer engineering curriculum. In the fall semester of 2011, we selected a CPLD as the choice of PLDs for the introductory logic circuits course, because CPLDs allows for an experience that includes modern design tools and devices, as well as hands-on activities. Our CPLD module allows such a device to be used with a classic breadboard. In prior research we found that in using this module, students can easily identify the CPLD and with modest wiring they can construct circuits that they feel are both satisfying and engaging. In this paper, the most recent developments, which include both software and hardware upgrades, along with student feedback, are documented. With the Xilinx XC9536 CPLDs now obsolete we adopted a newer CPLD, and designed a new logic circuits trainer. The newer XC9536XL CPLDs require 3.3V signals and power, which is not compatible with any commercially available trainer that we are aware of. Facing this inevitable trend to lower Voltage logic, we decided to adopt the 3.3V CPLD devices and design our own trainer that provides 3.3V power and I/O signal. The artwork for the module and trainer are available at our webpage under free software license for your use. On the software front, we revised our tutorial and started having our students working with test bench files. The CAD software used in our labs was upgraded from Xilinx ISE Version 10.1 to Version 13.2. In the past, we specifically chose Xilinx ISE 10.1 32-bit version for its graphical test bench generator which is very convenient for students to use when performing simulation. Unfortunately, this feature is absent in the ISE 10.1 64-bit version as well as the subsequent versions of Xilinx ISE, including 13.2. On the other hand, version 13.2 is much more stable in comparison to version 10.1. In adopting version 13.2, we had concerns regarding how students would generate the simulation test bench, which involves modifying VHDL codes, since students do not learn to write hardware description language (HDL) in our introductory logic circuits course. Xilinx ISE provides an aid in generating a skeleton which our students are able to modify for their own use following the instructions in our revised tutorial. New lecture material was developed to help students understand these upgrades. Based on student feedback, we also provided some historical context with regard to the current state of the art in logic circuits. New lab content was developed to address some concerns from our previous experience, which include: a) start-up activities to help students master the CAD software better and earlier in the course; b) incorporating the use of hierarchical design earlier and in more experiments. The students' experience and feedback, as well as the instructors' observations are presented concerning both the hardware and software upgrades along with other changes made. In closing, we present our future plans. © American Society for Engineering Education, 2014.