Investigations on Driver and Layout for Paralleled GaN HEMTs in Low Voltage Application

Abstract

Gallium nitride is becoming more popular in low-voltage applications. Gallium nitride (GaN) high electron mobility transistors (HEMTs) has positive temperature feature. It makes parallel application feasible for GaN HEMTs. Meanwhile, paralleled GaN HEMTs will increase the power handling capability and the efficiency of the converter. The parasitic parameters of both driving and power loop layout are critical which need to be equalized and minimized in GaN HEMT parallel operation. The parameters mismatch of the parallel branch will lead to significant effect on the dynamic characteristics and bring thermal problem of the GaN HEMTs. This paper focuses on the design of paralleled low-voltage enhancement GaN HEMT, and evaluates the effect of the parasitic inductances in both driver and power loops. The LT-spice and ANASYS Q3D Extractor simulation are carried out to analysis the effect of the unbalance parameters. The design guidelines for driver and PCB design are summarized as well. Finally, a 300W isolated DC-DC converter is built to verify the analysis and simulation on parallel operation.