SPADES: A simulator for path delay faults in sequential circuits

Abstract

A fault simulator for path delay faults in synchronous sequential circuits is described, where a test sequence is considered under different combinations of slow and fast clock cycles (clocking schemes). The novel features of the simulator are: (1) multiple clocking schemes used for the application of a given test sequence are considered in parallel, allowing fast fault simulation for a given sequence, to obtain the highest fault coverage achievable by every sequence, (2) during the simulation process, it is possible to determine the clocking scheme so as to minimize the number of different clocking schemes to be used with the sequence, without compromising the fault coverage, and (3) a path representation scheme is used, that allows efficient access to path delay faults detected by previous tests. Experimental results are presented to demonstrate these features and their effectiveness.