A minimum area VLSI network for O(logn) time sorting extended abstract

Abstract

A generalization of a known class of parallel sorting algorithms is presented, together with a new interconnection to execute them. A VLSI implementation is also proposed, and its area-time performance is discussed. It is shqwn that an algorithm in the class is executable in O(logn) time by a chip occupying O(n-) area. The design is a typical instance of a "hybrid architecture", resulting from the combination of well-known VLSI networks as the orthogonal trees and the cubeconnected- cycles; it also provably meets the AT 2 = (n21og2n) lower bound for sorters of n words of length (l+s)logn(e 0).