A novel single event upset hardened CMOS SRAM cell

Abstract

This paper presents an improved design of a radiationhardened static random access memory (SRAM). The simulation results based on the 0.18 μm standard digital CMOS technology show that its static current drops dramatically compared with the WHIT cell, and the write speed is equivalent to that of other cells. The memory cell is extremely tolerant to logic upset as it does not flip even for a transient pulse with 100 times the critical charge of the ROCK cell. According to these features, this novel cell suits high reliability applications, such as aerospace and military. © IEICE 2012.