CMP Development for Ru Liner Structures beyond 14nm

Abstract

For better gap fill in beyond 56nm pitch Cu interconnect structures, Ru liner is one of the most promising solutions with better coverage and wettability. In this paper several new challenges in Ru CMP specific to ≤ 48nm pitch structures (also called 10nm technology) are presented. New CMP solutions were developed by optimizing the slurry, consumables, and process sequence to address the observed challenges such as Ru bending and Cu recess. The optimized solutions to address these challenges were further tested on integrated wafers and improvements in resistance and yield were demonstrated through electrical tests. Meeting the resistance target in back end of the line (BEOL) interconnects is increasingly challenging for sub-14nm technologies and there has been a continuous focus to find the right combination of barrier and Cu metallization. 1-6 For better gap fill in these fine dimension structures, new liner materials and wetting layers are required. 7-13 Co is a known wetting layer for Cu that enables void free metallization. However, for future technologies scaling Co thickness is challenging due to the loss of Co Cu plating solutions and CMP, resulting in sidewall voids and poor reliability. 7-10 Ru is also a good wetting layer for Cu. Ru has better corrosion resistance in Cu plating solutions compared to Co and is a good substrate for PVD Cu reflow fill processes. 11,12 With Ru, low line resistance and void free metallization has been achieved in sub 14 nm technologies. However, a major challenge to implementation of Ru in a semiconductor product is CMP. The industry does not yet have a CMP process that can planarize Ru liner and Cu without defects such as galvanic corrosion of Cu, dendrite formation, and interlayer dielectric damage. 14 Several researchers have studied Ru CMP. 15-19 CMP of this material requires novel slurries with strong oxidizers such as ceric ammo-nium nitrate, NaIO 4 , KIO 4 , KMnO 4 , etc. As an example, the reaction below shows the mechanism for potassium periodate as the oxidizer for Ru CMP. PH values greater than 8 are preferred for Ru CMP due to the formation of toxic (RuO 4) formation in the acidic and neutral pH regions. Ru + [IO 4 ] − + 2OH − ←→ RuO 4 2− + H 2 O + (1/2) O 2 + I − (pH ∼ 8 to 14) Many CMP studies have been conducted showing high Ru removal rates (RRs) both with and without tunable RR selectivity on Cu and dielectrics. Galvanic corrosion of Cu in Ru slurries has been a focus and indicates the need for corrosion inhibitors to minimize the corrosion potential difference between Ru and Cu. 20,21 These studies have primarily focused on blanket Ru polishing and ways to mitigate corrosion based on electrochemical data. In this study, we evaluate commercially available slurries on 48nm pitch (10nm) integrated structures with Ru liner. Critical challenges in planarizing Ru CMP are identified. Using experimental data, the defect mechanism and a mitigation path are shown. Experimental 300mm diameter wafers with 10nm dual damascene test structures were used for all CMP experiments. The barrier/liner materials for the test structures are TaN/Ru; TaN was deposited by physical vapor deposition (PVD) and Ru was deposited by chemical vapor de-position (CVD). After barrier/liner deposition, a PVD Cu seed was z E-mail: rrpatlol@us.ibm.com deposited, followed by approximately 4500 Å Cu overburden using electrochemical plating. Cu CMP was performed using slurry Z. Barrier CMP was performed with slurry A, slurry B, slurry C or slurry B+C (the last using a two step barrier/liner process). In this experiment, slurries Z and A are commercially available silica abrasive Cu and barrier/liner slur-ries respectively. Slurries B & C are silica based new formulations. Cu CMP was processed on platen 1 (P1) based on an end-point system followed by overpolish to clear the residues. The same Cu slurry was used throughout the experiment. Barrier/liner CMP was a timed polish, processed either on platen 2 (P2) for the single step process, or on P2 followed by platen 3 (P3) for the two-step process. Slurries A, B and C were evaluated as single step barrier/liner CMP processes. In addition, slurries B and C were tested as a two-step process with slurry B on P2 followed by buff CMP with slurry C on P3. Further details on the slurry and polish conditions are shown in the Table I. Post CMP clean was performed after barrier/liner CMP with an alkaline cleaning chemistry followed by DIW rinse and dry. The same cleaner chemistry was used on all wafers. Post CMP, wafers were inspected by Scanning Electron Mi-croscopy (SEM), Transmission Electron Microscopy (TEM) and Energy-Dispersive X-ray (EDX) to study and understand Ru CMP defectivity. Electrical test data was collected to compare electrical leakage and resistance data for the different polish conditions. Results and Discussion Some of the key challenges identified in our Ru CMP development work are recess of Cu lines and Ru bending. These two issues significantly degraded the electrical performance resulting in high resistance and poor reliability. These problems were not observed in 56nm or 64nm pitch structures of prior node technologies. Figure 1 shows a post CMP cross sectional image of 56nm and 48nm pitch structures. Figure 2 shows a post CMP cross sectional image, STEM/EDX of a Cu line showing both Cu recess and Ru bending. With the same liner thickness, Cu recess and Ru bending are seen to occur in the narrower dimension structures of 48nm pitch and below. On the same wafer, wide lines ≥ 2X the minimum pitch did not exhibit similar problems. To identify the root cause of these issues, we started with liner CMP time splits, including a Cu only CMP split (zero time in liner CMP). The object was to gradually increase the polish time to understand the behavior of the liner/barrier CMP. Figure 3 shows that there is a large recess after the P1 step, Cu CMP. The liner/barrier is also intact in the field region, as the Cu slurry is highly selective to liner/barrier materials. After an initial polish of X seconds on the barrier step the Cu recess stays almost the same. With increasing polish times on subsequent wafers with X+ seconds and X++ seconds, the liner/barrier in the field region is cleared and the Ru begins sticking out with reduced Cu line height (dielectric removal), eventually resulting in bending of the vertical Ru film.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 210.107.218.170 Downloaded on 2018-11-06 to IP