Scaling floating-gate devices predicting behavior for programmable and configurable circuits and systems

Abstract

This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG circuits in scaled down processes in a way predictable through MOSFET physics concepts. Scaling FG devices results in higher frequency response, (e.g., FPAA fabric) as well as lower parasitic capacitance and lower power consumption. FPAA architectures, limited to 50-100 MHz frequency ranges could be envisioned to operate at 500 MHz-1 GHz for 130 nm line widths, and operate around 4 GHz for 40 nm line widths.