Platform for Model-Based Design of Integrated Multi-Technology Systems

Abstract

Until recently, the single recognized vector enabling the improvement of the silicon system performance was perceived to be the progressive reduction (scaling) in CMOS device dimensions. Popularly known as Moore’s law, this trend will lead to the emergence of transistors of physical gate lengths of 10-18 nm in the 2010-2015 timeframe, according to the predictions of the ITRS.* Consequently, the complexity of systems on chip (SoC) will reach unprecedented levels (high-performance microprocessors already contain over 109 transistors). However, the pursuit of Moore’s law through scaling will meet significant future, intrinsic device hurdles (such as leakage, interconnect, static power, quantum effects) to the capability of realizing system architectures using CMOS transistors with the performance levels required by future applications. It is recognized that these limitations, as much fundamental as economic, require the semiconductor industry to explore the use of novel devices able to complement or even replace the CMOS transistor in SoC within the next decade.