Design and Analysis of Ferro Electric-Tunneling Junction-VTFET for RF/Analog and Linear Application

Abstract

In this paper a new ferro material embedded structure is introduced between the tunneling junction to gain and improve ON/OFF current ratio with steeper subthreshold slope. Various linear and RF/analog device characteristics has involved to evaluate and validate the device suitable for low power digital and analog applications. The prime focus is to analyze the impact of ferroelectric layer at tunneling junction on the Id-Vgs characteristics and compared it with the conventional vertical TFET and Ferroelectric oxide material Vertical TFET to differentiate the electrical parameters performance thorough TCAD simulation Silvaco software. The vertical arrangement of source channel and drain will improve the geometrical scaling of the device. The RF/analog parameters like transconductance (gm), output conductance (gd), gate capacitance (Cg), cutoff frequency is varied with respect to the ferroelectric thickness at tunneling junction. For different configuration of TFP, linear properties such as gm2, gm3, VIP2, VIP3, IIP3 have been investigated. It has been discovered that as the FE at tunneling junction will decrease the linear properties as well. This means that when the tunnelling ferro thickness is scaled down from high to low to source-channel interface, linear behavior will be inhibited and the RF/analog factor will improve. In compared to the Conventional VTFET and Ferro VTFET, the ON/OFF ratio showed improved results. The device was found to be suitable for low-power applications based on its performance. Because of the increased gain for TGF and TFP for low gate voltage biassing, it is widely used in low RF/analog applications.