Designs protracted to combinational and sequential circuits by using hybrid MOS transistor with memristor

Abstract

A resistive device with a memory characteristic feature entitled memristor is explored to overcome the limitations of the Complementary Metal Oxide Semiconductor (CMOS) technology scaling. The memristor is utilized in place of the Metal Oxide Semiconductor (MOS) transistor due to its non-volatile character and nano-scale element. Thus, researchers worked on a combination of memristor and MOS transistor affords with reduced area exploitation, reduced power dissipation, reliability, and large density. At this juncture, the design of an XOR gate with P-channel Metal Oxide Semiconductor (PMOS) transistors and memristors is accomplished. This design is implemented in 90nm CMOS technology in Cadence Virtuoso and simulations are brought about Spectre. The power dissipation and delay are reduced when compared with conventional CMOS XOR gate. Finally, it is used in full adder design. The average power dissipation is reduced by 69.32%. Further, some of the combinational and sequential circuits like 8×1 Multiplexer (MUX), 1×8 De-multiplexer (DEMUX), and 4-bit Universal Shift Register (USR) are developed. The power of 8×1 MUX is reduced by 43.7 % and the power of 1×8 DEMUX is decreased by 30 % when compared with the conventional designs. The sequential circuit of 4-bit USR is also designed and power is limited by 10.76%. The delay is improved by 79.39% for the proposed 4-bit USR. Improvement of power and delay is observed when compared with the traditional designs.