Design: High-Speed Block-Based Carry Speculative Adder for Error-Tolerant Applications

Abstract

While compared to exact adders, approximate adders have a shorter propagation time and take up less space. For the approximate computing, we use two alternative strategies. The adder is split into certain non-overlapped summation blocks throughout the first structure, and also the substitute adders employed which is called as Knowles parallel prefix adders. The propagation delay will be reduced by implementing the Knowles adder construction. Full adder sum is built with one or gate and single x-or gate in the next structure. The amount of space available will be decreased as a result of this design. In terms of time and area, the novel method is compared with the previous method.