Analysis of a square parasitic antenna by using Lumped elements

Abstract

In This paper, a novel approach to design a parasitic antenna for an RFID application. This approach is based on using a parasite square patch near to a square patch. The square antenna is simulated by using HFSS and ADS and the proposed parasitic antenna is developed by using Lumped elements. This antenna can be integrated in an RFID TAG by using the electrical model of both antenna and IC. The size of antenna is 31mm*31mm*8.5mm.