Design of low power hybrid gaincell-e DRAM for embedded processors

Abstract

This brief mainly focuses on increasing the data retaining capability at the Storage Node (SN) and reducing the power consumed by the Hybrid Gaincell eDRAM/SRAM (HGC-eDRAM/SRAM). A Hybrid Gaincell eDRAM/SRAM cell contain SRAM cell and DRAM cell. Both the SRAM and DRAM cell share the SN. The DRAM cell here is implemented as 3T Gaincell. The data retaining capability is improved by isolating the shared SN of the SRAM cell and adding a capacitance at the SN if the 3TGaincell. The above-mentioned modifications are implemented in Cadence Virtuoso 6.1.6 using 90nm technology.