Realization of FIR Filter Using Modified Distributed Arithmetic Architecture

Abstract

This paper presents an efficient implementation of Finite Impulse Response Filter (FIR) using Distributed Arithmetic (DA) architecture. Here, the multipliers in FIR filter are replaced with multiplierless DA based technique. The DA based technique consists of Look Up Table (LUT), shift registers and scaling accumulator. Analysis on the performance of various filter orders with various partitions on different address length of partial tables are done using Xilinx 12.3 synthesis tool. The proposed architecture provides an efficient area-time-power implementation which involves significantly less latency and less area-delay complexity when compared with existing structures for FIR Filter.