A 0.5 v 1.28-MS/s 4.68-fJ/conversion-step SAR ADC with energy-efficient DAC and trilevel switching scheme

Abstract

This paper describes a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient trilevel alternate switching capacitive digital-to-analog converter (CDAC). The switching scheme of this CDAC preserves the features of the asymmetric-switching CDAC. By narrowing and smoothing the dynamic variation of DAC voltage, the switching scheme diminishes the dynamic offset effect induced by the asymmetric-switching CDAC. The CDAC reduces the capacitor requirement by almost fourfold and improves the average switching energy efficiency by almost 86.5% when compared with the conventional switching CDACs. This SAR ADC was implemented using the 90-nm CMOS technology, and its measured performances were as follows: 1) spurious free dynamic range of 56.98 dB; 2) signal-to-noise-and-distortion ratio of 68.79 dB; and 3) power dissipation of 3.45 μW at an operation of 0.5 V and 1.28 MS/s. The ADC achieves a figure-of-merit of 4.68-fJ/conversion-step.