On floorplans of planar graphs

Abstract

Floor-planning is an early step in very large scale integration (VLSI) design where a designer decides the location of functional entities of a circuit on a chip. A floor-plan is a rectangle partitioned into a set of disjoined rectilinear polygonal regions called modules. A floor-plan represents a plane graph for each vertex of the graph corresponding to a module of the floor-plan and the vertices are adjacent to the graph if and only if the corresponding modules share a common boundary. The quality of the final VLSI chip design depends on the on the quality of the floor plan. It is very desirable to use modules whose shapes are as simple as possible when constructing floor plans of planar graphs.