Improving the speed and power of compilable sram using dual-mode self-timed technique

Abstract

A long bitline precharge time in the write operation and a wide wordline pulse width in the read operation dominate the cycle time of large-capacity compilable SRAMs. A data-dependent bitline leakage current causes timing skew and erodes the sensing margin of conventional replica-column controlled embedded SRAM. A dual-mode self-timed (DMST) technique is proposed to generate two individual timing for the read and write operations, unlike in conventional SRAMs, in which they have the same control timing, to reduce the cycle time and power consumption of the SRAM. The RC delay on bitlines, variations in the write response time of a bitcell and data-dependent bitline leakage current are considered in the DMST. The DMST technique reduces the cycle time and the write active power consumption by 16%-30.7% and 15%-22.7%, respectively for a 65nm 512Kb SRAM. ©2007 IEEE.