Integrated power and clock distribution circuits in a wired and wireless clock network

Abstract

Integrating power with clock distribution networks is necessary to reduce consumption of power in a system on chip(SoC). This paper presents a novel circuit which integrates power with a clock distribution network. A CMOS oscillator circuit has been designed to generate an integrated power clock signal to drive the combinational part of a circuit. A clock buffer circuit based on a schmitt trigger is developed to convert the integrated power and clock signal into a full swing signal for driving the sequential part of the circuit. The simulation results obtained for the circuit show power consumption of 2.5uW which is lesser as compared to Integrated Power and Clock Distribution circuits (IPCDN) and Globally Integrated clock and power distribution circuits. The overall power dissipation in the proposed circuit is 60.9% lower than IPCDN circuit. The frequency obtained is 5 GHz and a voltage swing of 415mV is obtained by the circuit. The proposed circuit uses only 10 transistors as compared to 18 transistors used in IPCDN circuit and helps reduce the area and the total power consumption. To send out the clock signal in a wireless manner a CMOS based On-Off Keying modulator circuit is connected to the clock buffer circuit.. This circuit converts the clock signal into a wireless signal which can then be transmitted.