Distinguishing capture cross-section parameter between GIDL erase compact model and TCAD

Abstract

A compact model of 3D NAND enables simulation at circuit- or system-level. Although a compact model for gate-induced-drain-leakage (GIDL)-assisted erase was proposed in a previous study, it is difficult to use practically because it has not been properly validated. In particular, a capture cross-section (CCS) value that is far from the real value is used. Furthermore, it does not consider the latest device structure and its operation. In this paper, a conventional GIDL-assisted erase compact model is validated using TCAD and has been improved more practically. It is confirmed that we should distinguish between CCS in TCAD and the compact model due to their differences. Based on their physical differences, an equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering a tapered angle, single-side injection and word-line voltage is suggested.