A Proposed Cascaded Multilevel Inverter with R-Load at Different Carrier Frequencies

Abstract

Cascaded multilevel inverter has the major problem as voltage imbalance across the capacitors connected in circuits which are acting like dc sources. The number of level generation depends on the number of DC sources and switches placed in cascaded multilevel inverter topology. In this proposed topology the positive levels and zero levels of the inverter have been explained. This topology also work in symmetrical condition. The topology is simulated in MATLAB and its THDs are calculated at different modulation index. The voltage stress and loss calculations are carried out at different carrier frequencies.