A statistical characterization of dielectric breakdown in FDSOI nanowire transistors

Abstract

In this work, dielectric breakdown (BD) and post-BD conduction in ultimate FDSOI nanowire (NW) transistors with Ω-gate and high-k dielectric have been investigated. The experiments show that BD in largely scaled NW transistors differ significantly from that in bulk planar transistors. Several types of post-BD behaviours have been observed, some of which not only hinder the device performance, but also jeopardize the integrity of the nanowire structure and materials. A comprehensive study of the phenomena has been performed on pMOS and nMOS with different widths and lengths, under different temperature conditions.