16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects

Abstract

At nanometer nodes, process variability and BTI effect affect the SRAM design. Thus, SRAM design at 16nm must consider these impacts and explore alternatives to enhance SRAM robustness. Also, the advent of portable computing requires circuit with low power consumption. This work investigates the most used SRAM cell, 6T, and an alternative 8T cell to compare the effects of variability and aging on power, timing and noise margins, when operating in nominal and near-threshold supply voltage. Process variations showed up to 100% of deviation on 6T cell at near-threshold operation. Aging presented an improvement of about 175% of 6T RSNM at near-threshold operation after 5 years but reduces 10% at nominal operation.