A CMOS Floating Point Multiplier

Abstract

This paper describes a 32-bit CMOS floating point multiplier. The chip can perform 32-bit floating point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed point multiplication (two’s complement format) in less than 78.7 and 71.1 ns, respectively, and the typical power dissipation is 195 mW at 10 million operations per second. High-speed multiplication techniques—a modified Booth’s algorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder—are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2 μ m n-well CMOS technology; it contains about 23 000 transistors of 5.75 X 5.67 mm2 in size. © 1984 IEEE.