An efficient design of reversible subtractor in quantum-dot cellular automata

Abstract

Quantum-dot cellular automata (QCA) is a beneficial technology which is counted as one potential replacements for typical complementary metal-oxide-semiconductor (CMOS) archetype. QCA has excessive expedient thickness, particular performance speed with exceptionally low power depletion. Researchers have viewed plentiful devices of QCA based logic circuits though, yet not sufficient effort has been appraised on QCA based binary subtractor. This study outlined an optimized reversible binary half and full subtractors with power depletion analysis. The proposed reversible half subtractor has been designed using only 40 cells and occupied 0.0556 µm2 area. Besides, reversible full subtractor requires only 73 cells and occupies only 0.0831 µm2 areas. Moreover, the presented half and full subtractor dissipates only 36.78 meV and 81.56meV energy at 0.5 Ek tunneling energy level, respectively. The proposed circuits have been simulated and verified using QCADesigner, an extensively used simulation engine. The proposed layout can be operated to realize the nanoscale computing scheme in communication throughout minimal power utilization.