Design of Test Pattern Generator for Testing Crosstalk Faults in TSVs

Abstract

Design of Test pattern generator to test crosstalk faults in Through Silicon Vias (TSV) in three dimensional integrated circuits presented in this paper. A well-known test pattern generation model for testing crosstalk called as Maximum aggressor fault model is adopted in the design. The finite state machine diagram for design of TPG presented in reference [1] is modified and the complete design of TPG is discussed in this paper. Verilog HDL Simulation and synthesis results of the proposed Test pattern generator is discussed.