Incorporation of helium-implant-induced cavities near the active regions of metal–oxide–semiconductor devices: Effects on dc electrical characteristics

Abstract

Cavities, formed by helium implantation and subsequent annealing, have proved to be effective at trapping metal impurities within silicon. This has led to interest in their use as proximity gettering sites. In this investigation, cavity populations were formed by helium implants of energy 40 keV and dose 5×1016 cm−2 followed by annealing at 900 °C. This regime produces cavities with a mean void radius of 20 nm, located between 100 and 350 nm below the silicon surface. The effect of the presence of such cavities near the active areas of 1.2 μm p-type metal–oxide–semiconductor field-effect transistor devices is described. Electrical characterization of wafers, which have been implanted with helium on the front or rear silicon surface, has been carried out to determine whether the inclusion of void populations near the active regions of silicon devices is detrimental. These measurements found no evidence of any detrimental effect on the performance of working devices.