Adaptive Dead-Time Control Design with Low Dead-Time Error in 20 MHz 90 V GaN Gate Driver

Abstract

This paper presents an adaptive dead-time control circuit for a maximum work frequency 20 MHz, maximum voltage level 90 V GaN gate driver. The dead-time is set to prevent straight-through of the upper and lower power transistors of the bridge arm structure and ensure the reliability of the motor driver. For GaN drivers on the market today, fixed or configurable dead-time is widely used in more-than-10 MHz application scenarios. However, the switching loss caused by insufficient dead-time and reverse turn-on loss caused by excessive dead-time of GaN devices have a hazardous influence on the efficiency of drivers, which fixed or configurable dead-time cannot avoid. The gate driver with the proposed adaptive dead-time control circuit has been implemented in a 0.18 um BCD process. The proposed adaptive control circuit dissipates 56.3 uA quiescent current in a simulation situation and is able to provide maximum 5 ns dead-time error for a GaN gate driver.