Evaluation of a rack-scale disaggregated memory prototype for cloud data centers

Abstract

Disaggregated data centers propose a modular architecture where memory and compute resources are utilized in a finer granularity, aiming for a better optimized capacity and power consumption. In contrast to a classic compute node in a data center, memory is not required to be co-located with the processor, disaggregation can enhance hardware elasticity, improve virtual machine (VM) migration, and reduce the total cost of ownership (TCO), when compared to current data center solutions. This paper presents an evaluation of a disaggregated memory system prototype implemented on two modern FPGA SoC boards; one as a compute node and the second one as memory node. Using the PARSEC and Splash2x benchmark suites, we characterize our disaggregated prototype running on a remote memory node. In order to understand the design trade-offs, we utilize data collected from AXI Performance Monitors and break down the executions into three principal stages: (i) disaggregated memory address translation, (ii) network and (iii) memory access. This helps us to better evaluate the trade-offs of our prototype and to give better insight towards the next generation of disaggregated data centers.